Static Random Access Memory (SRAM) is often used in the cache of a CPU and in digital processing circuits where speed is an important requirement. In contrast to Dynamic Random Access Memory (DRAM), SRAM is more tolerant to radiation events than capacitor based DRAM.
An SRAM matrix includes arrays of individual SRAM cells. Each SRAM cell is addressed and accessed so that it may be “read” from or “written” to. Each SRAM cell includes a pair of cross-coupled inventers that are each used to store either a “high” or “low” voltage level. The cross-coupled inverters are coupled with a pass gate, such as a transistor, that allows the cross-coupled inverters to be read from or written to. Unfortunately, in radiation environments, such as space and aerospace, these cross-coupled inverters and other transistors are susceptible to radiation events.
Because SRAM cells are made from semiconductor materials, such as silicon, a radiation event, such as a particle strike, may create a radiation induced charge. This charge, or glitch, if large enough, may cause a node within the cross-coupled inverters to inadvertently change state. If a glitch results in a bit-flip or a change in state of the SRAM cell, it is referred to as a Single Event Upset (SEU) or a soft error.
One method that circuit and system designers use to prevent radiation events from causing an SEU in an SRAM matrix is to introduce a delay element in the signal path of an SRAM cell. For example, one SRAM cell 10, in a six transistor configuration, is illustrated in FIG. 1A. SRAM cell 10 includes inverter 12 cross-coupled with inverter 14. Inverter 12 includes Field Effect Transistor (FET) 16 coupled with FET 18. Inverter 14 includes FET 20 coupled with FET 22. The coupled drains of FETs 16 and 18 are coupled to an active delay 24. The active delay 24 is coupled to the gates of FETs 20 and 22 and it is enabled and disabled by respective delay and bypass signals communicated at delay input 25.
The SRAM cell 10, in operation, is written to and read from by data (bit) lines 26 and 28, FETs 30 and 32 (pass gates), and enable (write) input 34. When SRAM cell 10 is to be read, an enable signal is communicated to enable input 34 and it is used to open a conduction path between the drain and source terminals of FETs 30 and 32. In addition, throughout the read, active delay 24 is enabled. The voltage stored by the cross-coupled inverters at nodes 36 and 38 is then communicated respectively to data lines 26 and 28. The voltages on data lines 26 and 28 are data signals, where the data signal on signal line 28 is an inverse of the data signal on signal line 26.
When the SRAM cell 10 is to be written to, the enable signal is communicated to enable input 34 and active delay 24 is disabled. Output drivers, also coupled to bit lines 26 and 28, are used to drive the voltages at nodes 36 and 38. For example, if the voltage at node 36 is “low” and a “high” value is to be written, a high voltage is communicated by the output driver to node 36. Node 36 drives the gates of FETs 20 and 22 so that a low voltage is produced at node 38. The low voltage at node 38 is used to drive the gates of FETs 16 and 18 so as to set the voltage at node 36 high. After the SRAM cell 10 is written, a disable signal may be communicated to enable input 34 and the SRAM cell 10 will store the voltage at nodes 36 and 38 until a write operation is performed again.
Without delay 24, the SRAM cell 10 would be more vulnerable to radiation events, including particle strikes. For example, if a glitch occurs on one of the nodes within SRAM cell 10, it could cause a glitch to propagate through the SRAM cell 10. An SEU may occur if the voltage stored at nodes 36 and 38 is inverted. The delay 24, however, prevents the SEU by driving a node that has been affected by a glitch back to its correct voltage level before the glitch is propagated through the delay 24.
An example of SEU prevention is demonstrated as follows. If the voltage at node 38 is low, for example, a glitch may cause the voltage at node 38 to go high. This high voltage will drive node 36 low. Delay 24, however, will continue to drive the gates of FETs 20 and 22 so that node 38 returns low. Delay 24 effectively delays the switching, or response time, of the cross-coupled inverters. If the response time is greater than the time it takes for the radiation induced charge to dissipate (i.e., the recovery time), the SRAM cell 10 has been effectively radiation hardened. When a delay signal is communicated to input 25, the response time of cross-coupled inverters 12 and 14 is increased. Alternatively, when a bypass signal is communicated to input 25, the response time is decreased. The bypass signal is generally used to decrease the delay of the SRAM cell 10 when it is being written to. The delay and bypass signals are used to optimize both the write speed and radiation hardness of the SRAM cell.
Active delay 24 generally includes elements that are used to increase or decrease the delay time of the cross-coupled inverters 12 and 14. For example, as shown in FIG. 1B, active delay 24 may include a FET 46 coupled with a resistance, such as a resistor 48. The FET 46 and resistor 48 may be coupled to receive the delay and bypass signals. When a bypass signal is communicated, the voltage at node 36 may be propagated through FET 46 (bypass path) to the gates of FETs 20 and 22. If a delay signal is communicated, however, FET 46 may close and the voltage at node 36 will be delayed for a finite amount of time by resistor 48 (delay path). The response time of the SRAM cell 10 may be tailored by adding additional elements to the delay or bypass paths of the active delay 24. For example, a capacitance may also be coupled with resistor 48.
Despite the effectiveness of current active delay schemes in current SRAM cells, however, current SRAM matrices bypass the active delays of multiple SRAM cells when a single SRAM cell is being written to. All of the SRAM cells in a particular row, for example, may have their active delay disabled when only one SRAM cell within the row is being written to. As a result, vulnerabilities to radiation events and other soft error phenomena still exist. Therefore, it would be desirable to design an SRAM matrix that reduces such vulnerabilities.